发明名称 COMPUTER SYSTEM AND VIDEO DECODER USED IN THE SYSTEM
摘要 PROBLEM TO BE SOLVED: To exclude a repeat field from a field composite processing object only by adding simple hardware logic and to display a smooth image without fadering on a display monitor of a computer. SOLUTION: A mask circuit 503 of a DVD decoder 112 inputs a repeat first field flag register (Rep-Reg) 112b in every Vsync that is outputted from a video port control circuit 502 and when a repeat first field flag = '1', it masks Vsync and Hsync which correspond to the next field. It automatically frees the mask when the next Vsync comes. A VGA controller 113 does not capture video data while the Vsync and Hsync are masked. Then, a repeat field is easily excluded from a field composite processing object.
申请公布号 JPH10322663(A) 申请公布日期 1998.12.04
申请号 JP19970127398 申请日期 1997.05.16
申请人 TOSHIBA CORP 发明人 ISHIBASHI YASUHIRO
分类号 H04N5/93;H04N5/92;H04N7/01;H04N7/24;H04N19/00;H04N19/44;H04N19/46;H04N19/59;H04N19/70;H04N19/85 主分类号 H04N5/93
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