| 摘要 |
The invention provides a test pattern selection method for testing of an integrated circuit which can achieve a high fault coverage using a small number of patterns and minimizes the total testing time. From within a test pattern file which includes L test patterns, N test patterns are read out as a set of temporarily selected patterns, and a fault coverage according to the combination of the N temporarily selected patterns is calculated. Then, one of the other test patterns is successively substituted into one of the N temporarily selected patterns and a fault coverage is calculated for each combination of test patterns. Then, N test patterns of a combination which exhibits the highest one of the fault coverages calculated in this manner are determined as finally selected patterns.
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