| 摘要 |
A digital signal processor on an integrated circuit uses a multi-port data flow structure characterized by four ports, referred to as an acquisition port, two data ports, and a coefficient port. All four ports may be bidirectional so that data may be read from and written to the respective ports by the DSP system. This architecture allows a data flow management scheme in which data enters the processor through the acquisition port, or any one of the data ports. As the data is processed, it may ping pong between the data ports, or between a data port and the acquisition port. At the end of a DSP algorithm, the output data may be provided through the acquisition port or a data port as suits the needs of the particular application. A coefficient port is typically used for providing coefficients or twiddle factors for DSP algorithms. A DSP system is provided which includes a digital signal processor having four ports as discussed above. Each data port is attached to dedicated, independent data memory. This provides for optimization of multipass algorithms.
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