发明名称 Method for fabrication BiCMOS integrated circuit
摘要 A first photoresist layer has opening portions in a region where an n-channel MOS transistor should be formed and in a region where a collector leading region should be formed. Then, phosphorous is implanted with taking the first photoresist layer as a mask. The first photoresist layer is then removed and a second photoresist layer is formed. The second photoresist layer has opening portions in a region where an emitter region should be formed and in the region where the collector leading region should be formed. Phosphorous is implanted with taking the second photoresist layer as a mask to form an n-type selective diffusion region in a region below the region where the emitter region should be formed and in the region where the collector leading region should be formed. Then, the second photoresist layer is removed. A polycrystalline silicon layer is formed over the entire surface and arsenic is implanted therein to make it n-type. Thereafter, heat treatment is performed to form an emitter region in the region where the emitter region should be formed and an n-type diffusion layer in the region where the collector leading region should be formed.
申请公布号 US5840603(A) 申请公布日期 1998.11.24
申请号 US19970915405 申请日期 1997.08.20
申请人 NEC CORPORATION 发明人 SAKAMOTO, KAYOKO
分类号 H01L27/06;H01L21/8249;(IPC1-7):H01L21/823 主分类号 H01L27/06
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