Dual damascene process for integrated circuits

摘要

Making an integrated circuit with first (78) and second (76) level conductor structures comprises: (a) providing a substrate (50) with integrated circuit device(s); (b) providing an interlayer dielectric layer (52) over the substrate; (c) providing an etch stop layer (54) over it; (d) patterning the etch stop layer to define openings corresponding to positions where first level conductor structures are to be formed; (e) providing an intermetallic dielectric layer (58) over the patterned etch stop layer; (f) forming a second level mask over the intermetallic dielectric layer; this mask having openings corresponding to positions where second level conductor structures are to be formed; (g) etching through the openings in the second level mask to form second level conductor openings in the intermetallic dielectric layer; (h) etching through the openings in the patterned etch stop layer to form first level conductor openings in the interlayer dielectric layer; the edges of the openings have a tapered configuration; they provide for a step-free transition with the second level conductor openings; and (i) depositing metal into the first and second level conductor openings.