| 摘要 |
A system for recovering most recent writer status when a mispredicted branch occurs in a processor that executes instructions out of order. A queue holds instructions stored in the order they are fetched from memory. Each slot in the queue stores a target register that will receive the results of the instruction, and a most recent writer status bit indicating whether the slot is the last instruction to write to the target register. When inserting a new instruction, each slot compares the target register of the new instruction to its target register, and when a match occurs, the slot resets its most recent writer status, and stores the new instruction slot number as a target taker. When a mispredicted branch occurs, the slot compares the mispredicted branch slot to the target taker slot, and when the target taker slot is greater, the slot regains the most recent writer status. |
