| 摘要 |
A clock signal generator comprises a phase locked loop circuit and a voltage level converting circuit. The phase locked loop circuit is supplied with a control base clock signal and an input clock signal which has a first frequency. The phase locked loop circuit converts the input clock signal to generate a PLL output clock signal which has the second frequency. The input clock signal has one of binary values that has a voltage level which is similar to a reference voltage level of a reference voltage. The voltage level converting circuit is supplied with the PLL output clock signal, the control base clock signal, the reference voltage, and a voltage level control signal. The voltage level converting circuit converts, in response to the control base clock signal, the reference voltage, and the voltage level control signal, the PLL output clock signal to generate an output clock signal which has an output voltage level which is different from the reference voltage level.
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