发明名称 |
Integrated circuit device, semiconductor memory, and integrated circuit system coping with high-frequency clock signal |
摘要 |
An input buffer circuit includes a first amplifier causing a first change in an output signal by detecting a rising edge of an input signal, a second amplifier causing a second change in the output signal by detecting a falling edge of the input signal, and a feedback path feeding back the output signal as a feedback signal to the first amplifier and the second amplifier. The feedback signal controls the second amplifier such that a timing of the first change only depends on the first amplifier, and controls the first amplifier such that a timing of the second change only depends on the second amplifier.
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申请公布号 |
US5838630(A) |
申请公布日期 |
1998.11.17 |
申请号 |
US19970990999 |
申请日期 |
1997.12.15 |
申请人 |
FUJITSU LIMITED |
发明人 |
OKAJIMA, YOSHINORI |
分类号 |
G06F1/12;G06F1/10;G06F13/42;G11C7/06;G11C7/10;G11C11/401;G11C11/407;G11C11/409;H03K5/00;H03K19/0175;(IPC1-7):G11C8/00;G11C7/00 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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