| 摘要 |
A metal oxide semiconductor static random access memory (SRAM) includes NMOS transistors and resistor structures implemented without multiple polysilicon layers. According to a first embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors having transistor gates formed of a polysilicon layer and resistors formed of the same polysilicon layer. In accordance with a second embodiment, the SRAM cell comprises a plurality of appropriately interconnected NMOS transistors, a dielectric layer overlying the NMOS transistors, and polysilicon resistors passing through the dielectric layer to connect the NMOS transistors to a first metal layer. The dielectric layer, deposited on the NMOS transistors, defines holes exposing drain regions in the NMOS transistors. A polysilicon layer is deposited on the dielectric layer to fill the holes, and the excess polysilicon is removed.
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