发明名称 PN CODE RECEPTION CIRCUIT
摘要 <p>PROBLEM TO BE SOLVED: To accelerate the pull-in-resetting of PN code signal to be tested into a PN code generating circuit after the occurrence of overflow and to improve accuracy in the supervisory of temporary error such as bit deviation. SOLUTION: Relating to a PN code reception circuit 100 for testing a transmission line, a pull-in-resetting control circuit 5 is provided for outputting a pull-in-resetting control signal for controlling the pull-in-resetting of PN code signal 101 to be tested and a pull-in-resetting instruction signal for instructing a selective PN code signal to a selector circuit 1 based on an overflow signal 201. Besides, an overflow detection circuit 4 outputs an overflow count signal showing the number of non-coincident bits with which the PN code signal to be tested and a reference PN code signal are not coincident and when the number of non-coincident bits exceeds a predetermined threshold value, the pull-in-resetting control circuit 5 outputs the pull-in-resetting instruction signal.</p>
申请公布号 JPH10303868(A) 申请公布日期 1998.11.13
申请号 JP19970114562 申请日期 1997.05.02
申请人 NEC CORP 发明人 KANEKO HIROAKI
分类号 H04L1/00;H04L7/00;H04L25/02;(IPC1-7):H04L1/00 主分类号 H04L1/00
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