发明名称 SEMICONDUCTOR MEMORY DEVICE
摘要 PROBLEM TO BE SOLVED: To attain the performance improvement of peripheral circuit or improvement in the degree of freedom for wiring layout design by efficiently reinforcing the current capacity or wiring number of power supply line or signal line. SOLUTION: The power supply line or signal line can be arbitrarily extended by utilizing a bit line separating area. Upper layer wires MLL and MLR for bridge are provided while being extended from the terminal part of array to the central part of array and terminated near the border of left side and right side effective array and dummy areas 20L and 20R. On this layer, upper layer wires 46 (46L and 46R) for step relax are provided from the dummy areas 20 through an inter-layer insulating film 44 to a bit line separating area 18 at a connection part CN near the bit line separating area 18. Then, wires 66 (66L and 66R) are provided inside the dummy areas 20 along with the bit line separating area 18 while being electrically disconnected for wiring layers as many as the upper layer wiring for bridge and this is used as the power supply line for driving a sense amplifier.
申请公布号 JPH10303389(A) 申请公布日期 1998.11.13
申请号 JP19970122981 申请日期 1997.04.25
申请人 TEXAS INSTR JAPAN LTD;HITACHI LTD 发明人 TAIRA MASAYUKI;SUKEGAWA SHUNICHI;BESSHO SHINJI;TAKAHASHI YASUSHI;TAKAHASHI TSUTOMU;ARAI KOJI
分类号 G11C11/401;G11C11/407;G11C11/409;H01L21/8242;H01L27/108 主分类号 G11C11/401
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