| 摘要 |
<p>A processor (100) has a clock generator (102), a sleep pin that receives an external sleep signal, and a first interface circuit (104) coupled to the clock generator circuit (102) and the sleep pin. The clock generator circuit (102) generates a core clock signal (116) and a bus clock signal (118) in response to an external clock signal (122). When the external sleep signal is asserted, the processor (100) enters a sleep state when the core clock signal (116) and the bus clock signal (118) are in a first predetermined relationship with each other.</p> |
