The circuit processes binary input data using a square root algorithm to provide binary square root data at the circuit output, obtained by addition of a number of square root data elements (qi). Each transfer stage of the calculation circuit has a logic circuit (11) receiving the sqare root data element (q(i-1)) from the previous stage and a number of selection circuits (12A- 12F ; 13A-13C) receiving the logic outputs of the logic stage, selected to provide the next sqare root data element.
