| 摘要 |
In order to reduce memory requirements in a chip or for demodulating digital video broadcast signals comprising data modulated on a multiplicity of spaced carrier frequencies, the chip comprises: analog to digital conversion means for converting the broadcast signal to a series of digital samples, real to complex conversion means for converting each digital sample to a complex number value, Fourier Transform means 24 for analysing the complex number values to provide a series of symbol values for each carrier frequency, frequency control means 38, comprising means responsive to the output of said Fourier Transform means for producing a signal for controlling the frequency of the signal formed by said complex number values, wherein the frequency control means derives a common phase error signal from said series of symbol values, first and second delay means 80, 82 coupled in series to receive said series of symbol values from said transform means, and for providing delayed versions to said automatic frequency control means, first and second common phase error correction (CPE) means 302, 301 for receiving said common phase error signal, for correcting said symbol values from said transform means, the output of the first delay means being applied to the first CPE means and the output of the second delay means being applied to said second CPE means, channel equalisation means 72 for compensating for communication channel impairments for receiving directly the phase error corrected signals from said first CPE means, and third and fourth delay means 92, 94 connected in series and connected to receive the output from said second CPE means and applying delayed versions of the same to the channel equalisation means.
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