| 摘要 |
In order to buffer a succession of input data sets to produce a succession of output data sets, an input/output buffer memory circuit includes a plurality of internal memory elements (1), each having a memory capacity capable of memorizing each of the input data sets. An input port (2) and an input control circuit (3) write each of the input data sets in any one of the internal memory elements as an internal data set. At least one random access port (4) carries out a random access to any one of the internal memory elements to subject the internal data set of any one of the internal memory elements to an internal data processing as a processed data set. An output control circuit (6) reads the processed data set out of any one of the internal memory elements and delivers the read data set to an output port (5) as each of the output data sets. A switching control circuit (7) controls the internal memory elements to successively connect each of the internal memory elements to the input control circuit, the random access port, and the output control circuit. Preferably, the switching control circuit periodically switches, at a predetermined time interval, the internal memory elements so as to simultaneously carry out an output control for one of the internal memory elements, the random access to another one of the internal memory elements, and an input control for still another one of the internal memory elements a time in the predetermined time interval.
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