发明名称 |
Flash-erasable semiconductor memory device having an improved reliability |
摘要 |
A flash-erasable semiconductor memory device has a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on the floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
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申请公布号 |
US5835408(A) |
申请公布日期 |
1998.11.10 |
申请号 |
US19970985714 |
申请日期 |
1997.12.05 |
申请人 |
FUJITSU LIMITED;FUJITSU VLSI LIMITED |
发明人 |
AKAOGI, TAKAO;OGAWA, YASUSHIGE;KAJITA, TATSUYA;WATANABE, HISAYOSHI;YAMASHITA, MINORU |
分类号 |
G11C16/08;G11C16/10;G11C16/16;G11C16/30;G11C16/32;G11C29/00;H01L21/8247;H01L27/105;H01L27/115;(IPC1-7):G11C16/06 |
主分类号 |
G11C16/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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