Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems

摘要

Vector register circuitry is provided which includes a vector register file comprising at least one vector register having a plurality of elements, the vector register file further having at least one data port and at least one address port for accessing selected ones of the elements of the vector register. Address generation circuitry is provided coupled to the address port and includes an adder having an output coupled to the address port, a first element register having an output coupled to a first input of the adder and an element counter having an output coupled to a second input of the adder.