A self-timed interface (STI) in which a clock signal clocks bit serial data onto a parallel, electrically conductive bus and the clock signal is transmitted on a separate line of the bus. The received data on each line of the bus is individually phase aligned with the clock signal. The received clock signal is used to define boundary edges of a data bit cell individually for each line and the data on each line of the bus is individually phase adjusted so that, for example, a data transition position is in the center of the cell.
申请公布号
US5832047(A)
申请公布日期
1998.11.03
申请号
US19940261515
申请日期
1994.06.17
申请人
INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人
FERRAIOLO, FRANK DAVID;CAPOWSKI, ROBERT STANLEY;CASPER, DANIEL FRANCIS;JORDAN, RICHARD CARROLL;LAVIOLA, WILLIAM CONSTANTINO