Highly integrated low voltage SRAM array with low resistance Vss lines

摘要

An SRAM array configuration is disclosed. SRAM cells (102) are arranged in rows and columns. Cell rows (104a-104f) are each driven by a particular word line (132). Cell row pairs (108a and 108b) are supplied with a low power supply voltage (Vss) by a number of Vss connections 116 disposed parallel to the cell rows (104a-104f). The word lines (132) and Vss connections 116 are "strapped" by low resistance word line straps (110b-110e) and Vss straps (112a-112b). Both the word line straps (110b-110e) and the Vss straps (112a-112b) are substantially offset with respect to their associated word lines (132) and Vss connections 116, respectively. The Vss strap offset is accomplished with the use of a Vss line 140 that makes contact with the Vss connections 116 and further includes landing portions 120 which extend in the column direction and make contact with the Vss straps (112a-112b).