发明名称 EMULATION OF INTERRUPT CONTROL MECHANISM IN A MULTIPROCESSOR SYSTEM
摘要 <p>A multiprocessor computer (10) system that includes an emulation feature for lowest priority processor (20) software compatibility while providing fault tolerance includes first (CPU1) and second (CPU2) processors coupled to a system bus (12) that handles transmission of interruption messages within the system.</p>
申请公布号 WO1998048346(A2) 申请公布日期 1998.10.29
申请号 US1998007708 申请日期 1998.04.16
申请人 发明人
分类号 主分类号
代理机构 代理人
主权项
地址