| 摘要 |
The invention provides a phase synchronization system which stops, when an input of a phase reference signal from the outside stops, oscillation of a voltage-controlled oscillator to achieve reduction in power consumption and can produce and output a system clock signal free from high frequency pulse noise from the voltage controlled oscillator. The system includes a phase comparator, a phase synchronization circuit including a low-pass filter and a voltage-controlled oscillation circuit, a clock detection circuit for detecting the clock signal from the outside, a phase coincidence discrimination circuit for discriminating a phase coincidence condition at the phase synchronization circuit, an AND gate, and a stop/start control circuit including a pair of flip-flop circuits. When the clock signal from the outside stops, oscillation of the voltage-controlled oscillation circuit is stopped with control information from the stop/start control circuit. When the input of the clock signal is resumed, a phase synchronization signal from the voltage-controlled oscillation circuit is outputted to the outside via the AND gate after phase coincidence is discriminated by the phase coincidence discrimination circuit.
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