| 摘要 |
The pulsed reset single phase dynamic logic of the present invention reorders the conventional modes of operation such that in a single cycle of operation of a domino logic circuit, reset occurs first, followed sequentially by gap2, evaluation and gap1. To reset each domino stage prior to evaluating, a reset pulse is propagated to each domino stage, with an evaluate signal arriving at each stage as the reset pulse is ending. The circuit configuration of the present invention creates a different, but shorter and easier to manage set of race conditions. The present invention permits the creation of faster and more robust circuit designs.
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