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发明名称
SEMICONDUCTOR INTEGRATED CIRCUIT, ELECTRONIC CIRCUIT DEVICE AND INPUT/OUTPUT BUFFER TEST METHOD
摘要
申请公布号
JPH10285012(A)
申请公布日期
1998.10.23
申请号
JP19970088278
申请日期
1997.04.07
申请人
HITACHI LTD
发明人
ISEZAKI TSUYOSHI
分类号
G01R31/28;H03K19/00;H03K19/0175;(IPC1-7):H03K19/017
主分类号
G01R31/28
代理机构
代理人
主权项
地址
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