发明名称 |
Method and apparatus for preventing logic glitches in a 2/n clocking scheme |
摘要 |
A 2/N mode clock generator that generates bus clock signals through the use of bus clock enable signals selecting bus clock pulses that are in phase and out of phase with a core clock signal. The clock generator maintains synchronization between the bus clock signal and the core clock signal so that they are always in a predetermined phase relationship.
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申请公布号 |
US5826067(A) |
申请公布日期 |
1998.10.20 |
申请号 |
US19960709262 |
申请日期 |
1996.09.06 |
申请人 |
INTEL CORPORATION |
发明人 |
FISCH, MATTHEW A.;PATHIKONDA, CHAKRAPANI |
分类号 |
G06F1/12;(IPC1-7):G06F1/04 |
主分类号 |
G06F1/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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