| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a column selection line control circuit for a synchronizing semiconductor memory, a synchronizing type semiconductor memory, and its control method in which a time margin for writing input data inputted from the outside of a chip in a memory cell is increased. SOLUTION: A column selection line control circuit is provided with a column decoder 81 and a column selection line controller 82. The column decoder 81 drives a column selection line CSL 2i in accordance with a pre-decoded address DCAij, a column selection line-enable control signal PCSLE2, and a column selection line-disable control signal PCSLD2. The column selection line controller 82 receives an internal clock PCLKS and generates the column selection line-enable control signal PCSLE2 and a column selection line-disable control signal PCSLD2 in accordance with a first control signal P2N and a second control signal PWR with a writing cycle of pre-fetch structure to delay an enable-time and a disable-time of the column selection line CSL2i. The first control signal P2N is made active when a synchronizing semiconductor memory is operated as pre-fetch structure, the second control signal PWR is made active with a writing cycle.</p> |
