Back bias voltage detection circuit for semiconductor memory device

摘要

A back bias voltage detection circuit used for a semiconductor memory device wherein a threshold voltage of an NMOS transistor is varied by the back bias voltage. The threshold voltage of the NMOS transistor is detected by comparison to a reference voltage and the back bias voltage is adjusted according to the threshold voltage, with variable amplification of the back bias voltage. This control of the back bias voltage provides more effective control of the threshold voltage of the NMOS transistor.