| 摘要 |
A memory circuit is comprised of a prefetch predecoder, so that this memory circuit can be sequentially accessed by any addresses. The prefetch predecoder is interposed between an address buffer and a column decoder. Upon receipt of information for indicating lower-digit 3 bits of a column address and a burst length, the prefetch predecoder produces such a predecode address for representing both of a decoded result about this lower-digit 3 bits and another decoded result corresponding to the information indicative of the burst length. In response to a predecode address and an upper-digit bit of the column address, the column decoder simultaneously selects a plurality of column selection lines. As a consequence, both of data to be firstly outputted and data to be subsequently outputted are read out at the same time.
|
