| 摘要 |
PROBLEM TO BE SOLVED: To enable a semiconductor memory to reset contents of data of all memory cells at a high speed, and to shorten the time required for reset. SOLUTION: In a memory cell, one side of input terminals of a two input NAND circuit 9 is connected to an output terminal of an inversion circuit 8A, the other side of the two input NAND circuit 9 is connected to a reset line NRST, an output terminal of the two input NAND circuit 9 is connected to an input terminal of the inversion circuit 8A, one end of a N type MOS transistor 10A is connected to an output terminal of the inversion circuit 8A, the other terminal of the N type MOS transistor 10A is connected to a positive logic bit line BL, a gate of the N type MOS transistor 10A is connected to a word line WL, one terminal of a N type MOS transistor 10B is connected to an input terminal of the inversion circuit 8A, the other terminal of the N type MOS transistor 10B is connected to a negative logic bit line NBL, a gate of the N type MOS transistor 10B is connected to the word line WL, and a reset line of many memory cells is made common. |
