Superscalar microprocessor including a cache configured to detect dependencies between accesses to the cache and another cache

摘要

A microprocessor is provided including a pair of caches and a dependency checking structure for accesses between the pair of caches. One of the pair of caches is accessed from the decode stage of the instruction processing pipeline, while the other is accessed from the execute stage. The dependency checking structure monitors for memory dependencies between accesses to each of the pair of caches. Memory accesses may be performed earlier in the instruction processing pipeline than was previously achievable. Additionally, the dependency checking structure ensures that memory accesses receive the correct data by comparing accesses performed from each stage of the instruction processing pipeline to each other. In one embodiment, read and write dependency bits are stored by the cache which is accessed from the decode stage of the instruction processing pipeline. Decode stage accesses are recorded as a read or write by setting an associated dependency bit. When accesses are performed from the execute stage, the dependency bits are checked to determine if a dependency exists with respect to an access performed from the decode stage. Corrective actions are performed based on analysis of the dependency bits. Correct results are maintained for the cases in which dependencies exist by effectively forcing the accesses to occur in program order.