| 摘要 |
PROBLEM TO BE SOLVED: To improve quality of an output image by lowering a synchronous shift of a video signal to be outputted to an image recording section. SOLUTION: A condition of doubled video clock 2×VCLK at a time when a horizontal synchronizing signal/BD is inputted from a flipflop 101 is sampled to be held. A 1/2 dividing circuit 109 divides the clock 2×VCLK to generate a clock VCLK116. A parallel/serial converter 110 loads bitmap data 115 at an arbitrary timing and sequentially outputs a signal Video A 119 by executing serial conversion along the clock VCLK. A flipflop 104 samples the signal Video A at a trailing edge of the clock 2×VCLK to output a signal Video B which is delayed by a half cycle. When the clock 2×VCLK is in a level of 'H' at a time when the signal/BD is generated, a selector 111 selects the signal Video A and when it is in a level of 'L', the selector 111 selects the signal Video B to output a signal Video 118.
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