| 摘要 |
A circuit for holding constant the propagation delay time at an output terminal in response to an input signal having a varying transition time from one logic state to another logic state at an input terminal is provided. The circuit has a plurality of inverters, each inverter having an input node and an output node, connected in series between the input terminal and the output terminal. The circuit also has a first capacitive means coupled to one of the first inverter output nodes through a switch, and has a means coupled between the input terminal and the switch for engaging the switch to couple the capacitive means to one of the first inverter output nodes. The engaging means is timed to couple the capacitive means responsive to the transition time of the input signal whereby the propagation delay time at the output terminal is constant.
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