发明名称 |
Cache sub-array method and apparatus for use in microprocessor integrated circuits |
摘要 |
A cache sub-array method and apparatus for use in microprocessor integrated circuits. A processor unit is disposed within a central region of the microprocessor integrated circuit; a peripheral region is designated as a cache memory array region and surrounds the central region; a predetermined number of cache memory sub-arrays are placed in the peripheral region such that variable size cache memory arrays may be efficiently created. The cache memory sub-arrays contain a fixed fraction of a total cache word. The microprocessor integrated circuit itself has a modular cache memory array of variable size, and includes a central region having a processor unit disposed therein, a peripheral region designated as a cache memory array region surrounding the central region, and a predetermined number of cache memory sub-arrays disposed in the peripheral region such that the cache memory sub-arrays compose a modular cache memory array of variable size.
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申请公布号 |
US5812418(A) |
申请公布日期 |
1998.09.22 |
申请号 |
US19960742221 |
申请日期 |
1996.10.31 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
LATTIMORE, GEORGE MCNEIL;MASLEID, ROBERT PAUL;MUHICH, JOHN STEPHEN |
分类号 |
H01L21/822;G06F12/08;G06F15/78;G06F17/50;G11C5/02;H01L21/82;H01L27/04;(IPC1-7):G06F17/50 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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