| 摘要 |
1521414 Multi frequency signalling AMERICAN TELECOMMUNICATIONS CORP 19 March 1976 [11 April 1975] 11098/76 Heading H4R In a multi frequency signalling decoder for detecting the presence of one of a number of predetermined frequencies in each of at least two frequency bands, the input signal is applied to band pass filters 10, 12, Fig. 1, which select the frequencies in the respective frequency bands and apply the signals in the two bands to respective channels each of which includes a circuit 14, 16 for producing control pulses in substantial synchronism with the filtered signal, a time range quantizer which determines whether the filtered signal has, within predetermined limits, a period corresponding to one of the predetermined frequencies, a jitter detector which produces a gating signal which indicates whether jitter in excess of a predetermined jitter tolerance exists in the filtered signal, and an output gate which provides an output indicating the continuous, substantially jitter free, detection of predetermined frequency components in each of the frequency bands. As described the band pass filters are formed by active filters and the filter outputs are fed to limiters 14, 18, and period detectors 16, 20, which produce a first signal nPQT which is of duration substantially equal to a multiple, e.g. twice, the period of the input signal, and a second, enabling, signal MI n O which is "on" for the second half of the duration of the first signal. The signals nPQT and MI n O are applied to the time range quantizer 30, 32, Fig. 7, which comprises a counter 32 which is reset at the end of each "on" period of the signal nPQT and counts high frequency clock pulses Mc/4 during the "on" period to time the duration thereof. At predetermined count states of the counter in the quantizer, corresponding to the entry to and exit from count ranges corresponding to the limits on the valid duration of the "on" period of signal nPQT for each of the correct signalling frequencies an entry and exit point decoder 35 provides a switching signal to bi-stable 37 to provide a signal QrI when the count is within one of the valid ranges. Further register stages 38 and 39 provide output signals which enable identification of the particular range in which a valid output signal occurs. The counter 32 has a loop from its maximum count state to its input to prevent further counting once its maximum count has been reached without its being reset. Jitter in the input signal is detected by a shift register arrangement, Fig. 9 (not shown), which compares the states of the registers in the time range quantizer on successive counts and provides a "jitter free" signal when the register states are similar. The "jitter free" signals in each of the high and low bands are fed to timing and comparing circuitry 48, 49, Fig. 1, and Figs. 10 and 11 (not shown) where the presence of a "jitter free" signal lasting less than 21 mS is regarded as an interference component which can be ignored, an interruption in the jitter free signal lasting less than 35 mS is regarded as an interference component to be ignored, while an interruption in excess of 35 mS is accepted as an inter-signal pause or end of signal. |
