| 摘要 |
PURPOSE:To reduce the burden of a CPU when transmitting and receiving data. CONSTITUTION:This system is provided with a memory 28A, DMA part 24A and FIFO part 28B as transmission parts and memory 27A, DMA part 34B and FIFO part 27B as reception parts and when transmitted data are stored in the memory 28A by a CPU 34, them are transferred to the FIFO part 28B by the DMA part 34A. Thus, FIFO is performed, the data are transmitted to the side of a base station 1, when the data on the side of the base station are stored in the FIFO part 27B, they are read by the DMA part 34B in the order of storage, transferred to the memory 27A and processed by the CPU. Thus, the overwrite of received data caused by the processing delay of the CPU or the like is prevented.
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