发明名称 DESIGN AND METHOD FOR DESIGNING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 PROBLEM TO BE SOLVED: To easily calculate the area occupation rate of a layout pattern through the use of a conventional design rule check function. SOLUTION: A window frame is applied to the layout pattern which is automatically generated based on function design and logic design and which is composed of plural pattern elements by the AND operation of a frame pattern where a micro space is provided between the adjacent patterns and of the layout pattern, and the pattern is divided (step 104). Then, the pattern elements are made into one graphic by the OR operation of a grid pattern which is composed of micro line width and whose grid intervals are not more than the width of the pattern elements and of the divided layout pattern (step 105). The area of the layout pattern is obtained once by an AREA operation (step 106). When the area occupation rate is not adapted to a condition, a dummy pattern is arranged (step 109) and it is fed back.
申请公布号 JPH10247206(A) 申请公布日期 1998.09.14
申请号 JP19970049105 申请日期 1997.03.04
申请人 HITACHI LTD 发明人 KATO MASATAKA;WADA SHINICHIRO;KAZAMA HIDEO
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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