发明名称 Architectural power estimation method and apparatus
摘要 <p>A method (100) and apparatus (600) estimates power of an architectural design. Power functions are generated (step 102) for standard components (20) by synthesizing to a power-measurable implementation (step 202). A behavioral description is simulated (step 106) to produce switching activity and then parsed (step 108) to compute power from power functions of instantiated standard components (steps 109, 114, 118) from switching activity (step 116). Behavioral operations are parsed (step 108) into short and long blocks based on the number of operations. Short blocks are precompiled (step 110) to produce an RTL implementation including standard components. Power is estimated from switching activity at ports and inferred nodes (step 420). Long blocks are synthesized to produce power-measurable implementations (step 112). Power is estimated with a power function from weighted switching activity at each input (steps 508, 512-514). &lt;IMAGE&gt;</p>
申请公布号 EP0863470(A1) 申请公布日期 1998.09.09
申请号 EP19980103608 申请日期 1998.03.02
申请人 MOTOROLA, INC. 发明人 GAITONDE, DINESH D.;REYES, ALBERTO J.;XIE, HONGYU;RIGG, DANA M.
分类号 H01L21/82;G06F17/50;(IPC1-7):G06F17/50 主分类号 H01L21/82
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