Apparatus for generation of control signals from the read cycle rate and read speed of a memory

摘要

A computer system including a cache which has a wave pipeline read controller is described. The system in addition to the cache memory includes a processor coupled to the cache memory. The processor includes a register stack which stores values corresponding to a wave number and read speed which is loaded as part of a configuration of the processor. The processor determines a repetition rate for read data corresponding to a difference between the values of read speed and wave number. The processor includes a logic delay line comprised of a plurality of clock delay elements, each of said elements providing successively increasing discrete delays to a clock signal fed to the logic delay line. The delay line is used to provide inputs to a first and second multiplexer which are respectively controlled by a signal corresponding to a desired repetition rate for read cycles and a signal corresponding to the read speed of the cache memory. The delay pipeline permits address cycles to initiated earlier increasing data read bandwidth while reducing data valid windows.