| 摘要 |
In a data holding mode, a potential on a substrate region in a memory cell array is fixed at the same level as that in a normal operation mode, and an absolute value of a bias voltage applied to a substrate region in a peripheral circuit is made larger than that in the normal operation mode. When an operation mode changes, a memory cell transistor substrate potential does not change, and therefore a potential on a storage node of a memory cell does not change, so that the storage data is stably held. A threshold voltage of an MOS transistor in the peripheral circuit increases in absolute value, and a subthreshold current is reduced. A current consumption is reduced in the data holding mode of a semiconductor memory device without adversely affecting storage data.
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