| 摘要 |
A circuit for interfacing between the output voltage terminals of a focal plane array (FPA) detector and subsequent digital processing circuitry and employing a differential circuit including respective resistors to create first and second input currents and a control circuit to adjust the first and second input currents to eliminate the common mode current component. The control circuit includes a current source and a current mirror amplifier on each side of the differential circuit with each current mirror amplifier supplying a current sample signal to a current sense amplifier which, in turn, supplies a control signal to each of the current sources. The interface circuit accommodates input voltages of different polarities and magnitudes, while operating from reduced supply voltage levels and providing output currents limited within a defined range.
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