发明名称 MULTIPLE WRITES PER A SINGLE ERASE FOR A NONVOLATILE MEMORY.
摘要 A method of performing multiple writes before erasing a memory cell (500) is described. M bits are stored in a first group of levels of the memory cell. M subsequent superseding bits are stored in a second group of levels of the memory cell (550) without erasing the memory cell. Another method of writing to a memory cell includes the step of storing m bits in a first group of levels of the memory cell. A group indicator is adjusted to identify a subsequent group of levels of the memory cell. Next, m superseding subsequent bits are stored in the subsequent group of levels, without erasing the memory cell. The steps of adjusting the group indicator and storing m superseding subsequent bits are repeated. A method of deferring an erase for a memory cell is also described. A group indicator is adjusted to identify a group of 2m adjacent levels of the memory cell available for storing an m bit value. A method of reading a memory cell includes providing a group indicator. The group indicator identifies a group of 2m adjacent levels of the memory cell. An m bit value is then read by sensing the group of 2m adjacent levels identified by the group indicator.
申请公布号 MX9802298(A) 申请公布日期 1998.08.30
申请号 MX19980002298 申请日期 1998.03.24
申请人 INTEL CORPORATION 发明人 ROBERT N. HASBUN;FRANK J. JANECEK
分类号 G11C11/56;G11C16/10;(IPC1-7):G11C7/00 主分类号 G11C11/56
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