High-speed main amplifier with reduced access and output disable time periods

摘要

An output buffer is provided to output data read out from a memory array. The output buffer is composed of a main amplifier and an output driver. An input latch stage of the main amplifier is connected to an output of a preamplifier that reads out data from the memory array. A level shifter is coupled to the input latch stage to drive one of transistors in a transistor pair of the output driver. A driver stage is coupled to the input latch stage to drive another transistor in the output driver transistor pair. An output enable signal is supplied to the level shifter and to the driver stage to control the output driver. When the output enable signal is set to a first logic level, the output driver supplies valid data to an external device. When the output enable signal is at a second logic level, the output of the output driver is brought to a floating high-impedance state to disable data output.