发明名称 Data encoder/decoder for a high speed serial link
摘要 An encoder/decoder is disclosed which is operative to convert an 8 bit value to a ten bit serial run length limited code for transmission over a serial data link. The encoding technique maintains DC balance within 2 bits over a single ten bit word and compensates for DC imbalance by inverting selected words in the transmission sequence to correct for a DC imbalance resulting from the transmission of a prior unbalanced word. One or more encoding lookup tables are employed at the encoder to map each byte into a ten bit run length limited code for serialization and transmission over the serial data link. A second decoding lookup table is employed at the decoder to map the received 10 bit run length limited code into the original 8 bit value.
申请公布号 AU6042098(A) 申请公布日期 1998.08.25
申请号 AU19980060420 申请日期 1998.01.27
申请人 FUJITSU NETWORK COMMUNICATIONS, INC.;FUJITSU LIMITED 发明人 STEPHEN A. CALDARA;MICHAEL SLUYSKI;RAYMOND L. STROUBLE
分类号 H03M7/14;G06T9/00;H03M5/14;H03M13/31;H04L25/49 主分类号 H03M7/14
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