| 摘要 |
PROBLEM TO BE SOLVED: To suppress the increase in the phase difference of the center part and the edge part in widthwise direction of the gate electrode and the drain electrode of an FET (power FET chip), to suppress the lowering of maximum effective power, and to suppress the generation of lowering in power addition efficiency. SOLUTION: An FET 1 is fixed to the dielectric substrate 5 on a metal carrier 6, and a microscopic line is formed on the dielectric substrate 5. The gate electrode 2 and the drain electrode 3 of the FET 1 and the input/output upper electrode 7, having the width wider than the microscopic line, of the microscopic line are connected by a plurality of metal wires 4, and the length of the metal wires 4 is made longer as going to the center part from the edge part in widthwise direction of the FET 1. |
