| 摘要 |
PROBLEM TO BE SOLVED: To enable a bit line provided to a memory cell forming region of a semiconductor device to be lessened in parasitic capacitance and a signal wire provided to a peripheral circuit forming region to be lessened in parasitic resistance. SOLUTION: The memory cell forming region of a semiconductor substrate is covered with a photoresist film 10, an interlayer insulating film 9 provided to a peripheral circuit forming region is etched as deep as 300nm or so to be provided with a stepped part 300nm or so in height, and a silicon nitride film 11 is formed on all the surface of the substrate as thick as 100nm or so. Then, a groove patterned as a bit line and a signal wiring is provided to the interlayer insulating film 12 formed on all the surface of the substrate. After a contact hole 15 is formed as thick silicide (WSi) film or the like is formed as thick as 800nm or so on all the substrate, the conductive film is polished and filled in the groove, the surface of the conductor film is flattened, and a bit line 16A and a signal wire 16B are separately formed different from each other in thickness in the memory cell forming region and the peripheral circuit forming region respectively. |
