| 摘要 |
<p>An algorithmic pattern generator (APG) having extended register programming capability for use in a circuit tester. The APG is programmable to drive a subroutine memory in a tester. The APG may include a sequencer with paired loop counters, address generators having address and reference registers each paired with indexing registers, a data generator providing bit inversion with a latched inversion register, a topology memory, or a delayed access pipeline for data synchronization. The APG may also include a two stage address scrambler combining a crosspoint multiplexer and scrambler RAM. <IMAGE></p> |
