发明名称 |
Hierarchical fault modeling system and method |
摘要 |
A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierarchical logic circuit, a processor for processing the stored information relative to primitives and lower level fault models in the hierarchy for generating fault models for each succeeding higher level of design in the hierarchy, an input device for operator input of information to modify primitive fault models and a display subsystem for displaying various aspects of the hierarchical fault model generated in accordance with the present invention. |
申请公布号 |
US5796990(A) |
申请公布日期 |
1998.08.18 |
申请号 |
US19970929578 |
申请日期 |
1997.09.15 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
ERLE, MARK ALAN;GRAF, MATTHEW CHRISTOPHER;WOHL, PETER |
分类号 |
G01R31/3183;(IPC1-7):G06F11/263 |
主分类号 |
G01R31/3183 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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