| 摘要 |
PROBLEM TO BE SOLVED: To improve control efficiently for an elevator in speed within an extremely lower range. SOLUTION: An elevator speed controller comprises a speed detector circuit for counting clocks with its clock counter while its motor revolution pulse counter counts sets of signals obtained through the quadruplication is frequency of signals detected by its speed pulse detector to thereby detect the speed of an associated elevator on the basis of the set number counted by the motor revolution pulse counter and of the number counted by the clock counter; and a speed control amplifier for calculating the deviation of the detected speed value from a speed command value regarding their proportionals and integrals. If the detected speed value is not more than a predetermined value to the rated value, typically two percent value of the rated value in this case, in step S101, the speed controller switches the values set in the motor revolution pulse counter from existing integral multiples of four to those of integral multiple of one. That control enables the motor revolution pulse counter that otherwise recognizes to start operation upon at least four pulses to count only one pulse for an improvement in speed control performance for the elevator even to an extremely lower speed command. |
