| 摘要 |
In a memory access controller, request data is received from a selected request source, specifying the mode of access to a main memory (30), and is supplied to a first pipeline (50) in which it is periodically shifted along its stages. A second pipeline (51) is connected to the output stage of the first pipeline if request data at that stage indicates partial-write mode. Store data is also received during full-write or partial-write mode and stored into a source data register (21) and a buffer (22). A first controller (10) receives request data from the input stage of the first pipeline (50) for accessing the memory in a read mode if it indicates read or partial-write mode or accessing it in a write mode if it indicates full-write mode. The first controller (l0) further receives request data from the input stage of the second pipeline (51) and accesses the memory (30) in a write mode if it indicates partial-write mode. A second controller (31) examines request data from all stages of the pipelines (50, 51) to cause data read out of the memory (30) to be supplied to the request source if request data appearing at the output stage of the first pipeline (50) indicates the read mode. The data stored in the source data register (21) is supplied to the memory if request data appearing at the output stage of the first pipeline (50) indicates the full-write mode. If request data appearing at the output stage of the first pipeline indicates the partial-write mode, data read out of the memory and data waiting in the buffer (22) are merged and the second pipeline (51) is enabled to start periodically shifting request data along its stages. When this request data appears at the output stage of the second pipeline, the merged data is applied to the main memory.
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