发明名称 Address translator for a shared memory computing system
摘要 An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics address to a system address within the system memory. The invention initially partitions the system memory into a dedicated system memory for use by the graphics controller and a non-dedicated system memory for use by the central processing unit. The dedicated system memory corresponds to a base assigned memory within the graphics memory address map, and the non-dedicated system memory corresponds to a portion of the graphics memory address map excluding the base assigned memory. If the graphics address is within the base assigned memory, the graphics address is translated to a corresponding system address within the dedicated system memory. If the graphics address is within the portion of the graphics memory address map excluding the base assigned memory, the address translator converts the graphics address to a system address within the non-dedicated system memory, which designates a starting address of an available system memory block. Upon completion of the translation of the graphics address to the non-dedicated system memory, the boundary selector then selects a specific address within this allocated memory block corresponding to the graphics address.
申请公布号 US5793385(A) 申请公布日期 1998.08.11
申请号 US19960662057 申请日期 1996.06.12
申请人 CHIPS AND TECHNOLOGIES, INC. 发明人 NALE, WILLIAM H.
分类号 G06F12/02;(IPC1-7):G06F12/06 主分类号 G06F12/02
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