| 摘要 |
PROBLEM TO BE SOLVED: To reduce the capacity of a memory, the scale of a circuit and power consumption by controlling an address conversion circuit so that an address signal specifying a row address in writing operation is applied to a column decoder and an address signal specifying a column address is applied to a row decoder. SOLUTION: In a memory system 8, a write buffer 6 executes the writing operation of a prestage discrete cosine transformation(DCT) output in a memory cell array 2 and a read butter 7 executes the reading operation of a post stage DCT input from the array 2. Both the buffers 6, 7 can execute the writing/ reading operation of picture data in/from the memory cell array 2 simultaneously but mutually independently. The memory system has two-port memory constitution. Since the address conversion circuit 5 executes passing/switching operation alternately in each data block, data written in the memory cell array 2 as a two-dimensional array can be read out in a transposed state. |
